Multi-Core Computer Architecture · Instructor: Prof. John Jose
The time delay between two successive initiations of memory operation is called
What is the primary function of the Program Counter (PC) in a computer's CPU?
What is the name for the small, very fast type of RAM?
A 4GB byte addressable DRAM system needs a __ bits in its physical address
In a 5 stage RISC instruction pipeline, reading data from register file happens in
Which of the following hazards occurs due to true dependencies?
During an instruction fetch operation ___
A 2-way set associative cache of size 1KB has the block size of 32 bytes. If the system is using a 32-bit address, the the tag field has –
What is the reason for placing more than one word in a cache block?
What type of memory has to be refreshed constantly?
Given a direct-mapped cache with a size of 32 KB and a block size of 32 bytes, where the CPU generates 32-bit addresses, what are the number of bits required for cache indexing